1. Field of the Invention
This invention relates generally to data processing systems and, more particularly, to data processing systems having a master processing unit and at least one slave digital signal processing unit. An slave interface unit is inserted between the master processing unit and the digital signal processing units(s) to facilitate the exchange of data there between.
2. Background of the Invention
As the requirements for computational power have increased, one data processing system that has been increasingly employed to meet these requirements includes a master processing system that controls the operation of one or more slave digital signal processing units. The master processing unit, typically a general purpose microprocessor, has the flexibility to respond to a wide variety of conditions and provide an appropriate response. The digital signal processing units provide specialized capabilities that permit complex but repetitive tasks to be performed very rapidly. Thus, one or more slave digital signal processing units, operating under control of a master processing unit, can respond to a wide variety of computational-intensive requirements. However, the master processing unit and the digital signal processing unit are typically not directly compatible and may even be fabricated by different manufacturers. In order to permit the interchange of data between incompatible components or components which can exchange data with difficulty, standard signal protocols have been agreed upon to provide the requisite commonality. As an example, the asynchronous transfer mode defines signals that facilitate the exchange of data signal groups between a master processing unit and at least one digital signal processing unit. This protocol is provided for the Universal Test and Operations Interface for the asynchronous transfer mode (ATM) (UTOPIA) Level 2 Interface to conform to the ATM Forum standard specification af-phy-0039.000, as well as other applicable standards. The ATM cell or packet that is transferred in this protocol includes 53 bytes with a 5 byte header and a 48 byte payload in an 8-bit transfer mode, or 54 bytes with a 6 byte header and a 48 byte payload in a 16-bit transfer mode.
While the asynchronous transfer mode provides a convenient protocol for the exchange of data signals between the processing units, an interface unit must be provided to buffer the data signals. In addition to the transmit and receive functions that must be performed by the interface unit, a common configuration requires that one of the processing units operate in a master state while one or more other processing units coupled to the master processing unit has a slave status. Furthermore, the operational frequency of the processing units can have different clock frequencies.
The situation can be complicated still further in that each digital signal processing unit can have more than one processing units or cores associated therewith. In this situation, the data cells must be distributed efficiently among the plurality of processing cores.
A need has therefore been felt for apparatus and an associated method having the feature that an interface unit compatible with the asynchronous transfer mode is provided between a master processing unit and at least one slave processing unit. It would be a further feature of the apparatus and associated method that slave processing unit be digital signal processing unit. It would be a more particular feature of the apparatus and associated method that the slave processing unit be a digital processing unit with a plurality of core processing units. It would be yet a further feature of the apparatus and associated method to provide buffer storage unit capable of storing two data cells. It would be a still further feature of the apparatus and associated method to transfer data cells from the interface unit to the direct memory management unit on consecutive clock cycles. It would be a more particular feature of the present invention that the buffer storage unit be a first-in/first-out memory unit.